Re: architectural goals, Byte Addressability And Beyond

Anton Ertl wrote:

jgd@cix.co.uk (John Dallman) writes:

I would like to keep testing the commercial product I work on in a
big-endian, alignment-trapping environment.

Computer architecture exhibits convergence.  Starting in the 1960s it
converged on byte addressing with 8-bit bytes and on 2s-complement,
starting in the 1980s it converged on IEEE FP, and ending in the 2010s

Although we did not converge on doing denorms properly until the mid
2000s.
GPUs followed a more meandering path:: starting out with crappy but
fast
FP, then adopting IEEE containers, then over several generations
adopting
more and more of IEEE 754 semantics.
Then there are the SW (and a few HW) holdouts that still believe that
denorms are hard/slow and we need mechanisms to flush them from the
numerics. No, we don't, we need circuitry where denorms are not slower than norms without having slowed down the norms.

it converged on supporting unaligned accesses and on little-endian
byte order.  Your difficulties in getting hardware for testing whether
software can work with alignment restrictions and with big-endian byte
order is a result of that convergence.  Maybe your desire to keep your
software ready for big-endian hardware and hardware with alignment
restrictions is misguided.

New SPARC boxes are expensive, dealing with Oracle is hard work, and the
architecture has no future.

Ebay?

- anton