Re: Privilege Levels Below User

On Mon, 10 Jun 2024 18:52:06 +0200
Terje Mathisen <terje.mathisen@tmsw.no> wrote:

EricP wrote:
[snip]

Many processors automatically disable interrupts on trap because it
greatly simplifies the race conditions in their prologue and
epilogue. x86 did not disable interrupts on exceptions but x64
allows it as an option. 

 
I have written a lot of x86 interrupt handlers, these chips did very
much disable all interrupts when transferring control to my handler.
>

Intel's official terminology makes distinction between interrupts and
exceptions. The former are external/asynchronous, the later are
internal/synchronous. Exceptions are further sub-divided into faults,
traps and aborts.
Manual says that IF flag is cleared when interrupt is handled through
an interrupt gate. It is not cleared when interrupt is handled through
a trap gate. At that point  manual does not say that exception handled
through an interrupt gate also clear IF flag, but later on (in p.
6.12.1.2 in my copy of the manual) it says that they do.

The typical approach was to do the minimum work possible to save
whatever HW buffer/data needed saving, before executing a STI (SeT
Interrupt enable bit?) and then do anything else that had to be done
while still in the primary handler.
 
IRET restored flags, IP and CS, transferring control back to whatever
was running when the hw interrupt happened.
 
Terje