Re: Critical word first

Stefan Monnier wrote:

[...] is performed which *completely bypasses* the cache; [...]

Yes, critical word first.

How important is this nowadays?

With interconnect widths of ½ to 1 cache line per cycle, its utility
has
been significantly reduced.

From what I can tell, the bandwidth-time of transferring a whole cache
line is extremely short compared to the latency to the first word, so
I assumed that whether the critical word is send first or not wouldn't
make much of a difference.

When one has 64 cores on a die, the interconnect BW basically has to
be about 1 cache line per cycle.
If we have cores with a 1% miss rate in the L2 cache, every 100 cycles
we have to service 64 or more misses. So, you need a BW that big.
Then once you have to mux out any given word, you might just as well
hold the line and service outstanding requests from the buffer.
The more CPUs per die and the greater the instruction width per cycle,
the greater the BW of the cores<->memory interconnect.
When the width is lower, CWF is more important.

Is my intuition wrong?
Or is it simply that the difference is small but the cost is
even smaller?

When you can put 100 GBOoO cores on a chip, you should be able to
feed them at appropriate rates.

        Stefan