Re: Privilege Levels Below User

Scott Lurndal wrote:

 1) NMI are incredibly useful in certain cases, particularly for
in-kernel debuggers.
2) NMI is actually maskable on Intel hardware (in the chipset, not the
processor)
3) ARM refused to support NMI in Aarch64 (partially because they didn't
   have a spare exception vector).   They've backtracked and hacked in
a
   solution using the interrupt controller to create a
pseudo-unmaskable
   interrupt due to customer demand.

On an architecture where one has multiple simultaneous interrupt tables
(say 1 per Guest OS and 1 per HyperVisor) and each table manages 32K
individual interrupts each interrupt mask by its corresponding Enable
bit::
Can one NOT infer that; a SW convention to leave at least 1 enable bit always enabled, gives the system an NMI ??