Re: Privilege Levels Below User

On 6/12/24 8:22 AM, EricP wrote:

MitchAlsup1 wrote:

John Savard wrote:
>
>

After all, RowHammer is caused by multiple rapid-fire accesses to the
same address, or to related addresses, in memory.

>
Yes, the write buffer in my DRAM controller is the L3 cache. Modified
data in the L3 migrates towards DRAM as DRAM cycles permit, but there
is no way to cause a line to be continuously be written into DRAM.
If a modified line has migrated to DRAM, and it gets modified again
in the L3, that 2nd write will not be performed until a refresh cycle
on that DRAM is performed.
>
Thus if one tries to RowHammer My 66000 DRAM, DRAM gets refresh cycle
between each write.

 What does it do if L3 receives more writes than it has ways in a row,
does it stall evicts from L2?
 Lets say L3 is 4 way assoc and all four in a L3 row been updated,
then a 5th way in that same row is written from L2.
L3 has no place to hold that 5th way and it can't evict one
of the other 4 ways because that could cause rowhammer.

Sidenote: With skewed associativity, one can use cuckoo/elbow
caching, i.e., select a block for eviction from another "set"
(which could then select a block from a different "set" to
retain the block). (I prefer the term "cuckoo cache" because
it uses the same mechanism as "cuckoo hash", though "The Elbow
Cache: A Power-Efficient Alternative to Highly Associative Caches"
(2003, Mathias Spjuth et al.) may be the first publication
using the mechanism for processor caches. The concept is
sufficiently rarely referenced that no name is widely known.)
Skewed associativity already has a different concept of "set";
cuckoo replacement presents even more diverse replacement
options.
("Overlaid" skewed associativity would seem to increase the
chance that a better victim could be found sooner. Overlaid
skewed associativity — my term — was proposed for variable
page size TLBs in "Concurrent Support of Multiple Page Sizes On
a Skewed Associative TLB" (André Seznec, 2003).)
With more tags than blocks and at least some
indirection (e.g., "The V-Way Cache : Demand-Based Associativity via Global Replacement", Moinuddin K. Qureshi et al., 2005), the
effective associativity could be further increased.
(Victim caches are a more widely known way of "extending"
associativity.)

Seems to me that all it can do is stall the 5th write from L2 until
DRAM refresh rolls around and re-enables one of the pending L3 writes,
which would back up victim evicts from L2.
Or maybe L3 has a small fully assoc emergency overflow buffer,
but still that could fill up too.

Eventually writes would be stalled due to memory bandwidth even
with no avoidance of row hammering. Avoiding row hammer would
seem to cause extra delays in some cases, but that seems better
than changing data. (Quality of service/resource allocation
budgets might be important for avoiding denial of service given
resource sharing.)