Re: Qualcomm's Oryon boasts hardware "side-channel mitigations"

scott@slp53.sl.home (Scott Lurndal) writes:

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

https://images.anandtech.com/doci/21445/SDX_CPU_GPU%20Architecture%20Overview_15.jpg
>
Unfortunately, they don't describe what they do, and "mitigation" has
a weaker sound than "fix" to me, but maybe they mean a proper hardware
fix.  That would be the best case.  The worst case would be that they
just have added instructions or a special mode for disabling
speculation.

>
The Aarch64 architecture includes pointer auth, branch target ID,
Speculation barrier instructions, architectural features to prevent
exploitation of branch history buffers, and a few other features
intended to address many of the speculation related attacks.
>
I suspect that covers most of Qualcomms 'side-channel mitigations'.

That would be the worst case, then.

I hope that at some point (Hot Chips?) they will be more concrete
about what's behind their claims.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>