Sujet : Re: Qualcomm's Oryon boasts hardware "side-channel mitigations"
De : anton (at) *nospam* mips.complang.tuwien.ac.at (Anton Ertl)
Groupes : comp.archDate : 15. Jun 2024, 08:56:32
Autres entêtes
Organisation : Institut fuer Computersprachen, Technische Universitaet Wien
Message-ID : <2024Jun15.095632@mips.complang.tuwien.ac.at>
References : 1 2
User-Agent : xrn 10.11
mitchalsup@aol.com (MitchAlsup1) writes:
Anton Ertl wrote:
>
https://images.anandtech.com/doci/21445/SDX_CPU_GPU%20Architecture%20Overview_15.jpg
>
Unfortunately, they don't describe what they do, and "mitigation" has
a weaker sound than "fix" to me, but maybe they mean a proper hardware
fix. That would be the best case. The worst case would be that they
just have added instructions or a special mode for disabling
speculation.
>
Maybe they just followed my advice on deferring state updates until
after retirement.
Yes, that would be the best case (plus some cheaper fixes for some
narrower side channels: contention on resources shared between cores,
and timing of the misprediction recovery).
- anton
-- 'Anyone trying for "industrial quality" ISA should avoid undefined behavior.' Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com> 
Qualcomm's Oryon boasts hardware "side-channel mitigations"
Re: Qualcomm's Oryon boasts hardware "side-channel mitigations"
