Re: PCIe MSI-X interrupts

Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

One thing to note::
>
The PCIe root complex may send out an address, but when the
MMI/O receiver of said address then uses bits in the address
for routing purposes or interpretation purposes, it matters not that the sender did not know those bits were being used thusly--those bits actually do carry specific meaning--just not to the sender.

Said routing does not necessarily mean that the bits in
the addresses are interpreted in any specific way, if the
routing is done by a set of programmed range registers
(i.e. range X to X+Y is routed to destination Z,e.g. the
interrupt controller).

I was asking the contrapositive::
Is a system architecture allowed to define certain bits of
the translated address to be used as either routing or
indexing of a table that provides routing information.
Not as seen by request originator or request target, but
by the middle-men of transport ?