Re: Concertlina II: Full Circle

John Savard wrote:

On Tue, 18 Jun 2024 21:36:06 -0600, John Savard
<quadibloc@servername.invalid> wrote:

On Tue, 18 Jun 2024 23:57:54 +0000, mitchalsup@aol.com (MitchAlsup1)
wrote:

John Savard wrote:

>

And so you indicate this explicitly in VVM as well. I tended to assume
only a limited number of registers would be needed to live in, plus I
have both floating and integer register files, hence the differences.

>
It ends up that the majority of register uses in a loop do not need to
be visible outside of the loop. This is almost the contrapositive of
annotating which registers are temporary in the loop. 90%+ of loops do not even need the index register to be live outside of the loop.
>

You have convinced me here to learn from your wisdom: I will do two
things. One is to add a bit that decides whether my 1 bits (confined
to a single group of 8 registers) are live-in or live-out bits. The
other is to specify clearly to implementors that if a register is
specified as "live-in" but is never actually used in a loop, this must
not cause any problems.

I have not yet added my attempt at an imitation of VVM to Concertina
II. However, I have now laid some important groundwork for it.

In my architecture, there are already Cray-style long vectors. They
are intended to nbe the principal and most efficient way of working
with vector quantities in the architecture. So if my VVM-alike was
disjoint from them, and could only interact with them through memory,
this would be an awkwardness in the ISA that needlessly constrains
performance.

While the vectorizing HW certainly has CRAY-like vector flip-flops
they are not addressable by SW. The code within the VEC--LOOP brackets reads as if scalar:: So, My 66000 consumes exactly 2
OpCodes to provide an entire vector instruction set--one that
works as well as possible across various implementations.

So I've added operate instructions that allow operations where one
operand is in a normal register, and the other operand is in a
selected element of a vector register. The element is itself specified
by the contents of an integer register, for convenient use within
loops.

Thus, a VVM-alike loop, instead of going from some vectors in memory
to other vectors in memory, could go from some vector registers to
other vector registers. The vectors aren't virtual any more.

A VVM Loop is just a bunch of normal instruction between 2 brackets
that can be executed as fast as dependencies allow and as many times
as the loop count and condition allow.

John Savard