Re: PCIe MSI-X interrupts

Scott Lurndal wrote:

mitchalsup@aol.com (MitchAlsup1) writes:

Scott Lurndal wrote:
>

mitchalsup@aol.com (MitchAlsup1) writes:

Scott,

>

Note that the ECAM must support 8, 16, 32-bit (optionally 64-bit)
single-copy atomic accesses to all configuration space registers.

>
MMI/O is sequentially consistent while Config is Strongly ordered.
>
Exactly what are you intending to mean from "single-copy atomic
accesses" ??

It's a term-of-art in the ARM architecture document (DDI0487).

    A memory access instruction that is single-copy atomic has the
following properties:

    1. For a pair of overlapping single-copy atomic store instructions,
all
        of the overlapping writes generated by one of the stores are
        Coherence-after the corresponding overlapping writes generated
        by the other store.

Writes to a small local do not pass each other in the interconnect.

    2. For a single-copy atomic load instruction L1 that overlaps a
single-copy
       atomic store instruction S2, if one of the overlapping reads
generated
       by L1 Reads-from one of the overlapping writes generated by S2,
then none
       of the overlapping writes generated by S2 are Coherence-after the
       corresponding overlapping reads generated
       by L1.

Because the LD saw the intermediate data state where some of the STs
were
complete while others pend.