Re: PCIe MSI-X interrupts

EricP wrote:

MitchAlsup1 wrote:

Seems to me that if one is sequentially consistent, then one is also
multi-copy ATOMIC.

Yes, store atomicity to each locations would be implied by SC
otherwise how could all nodes agree on the order of all updates.

Most of the time cores only need to agree about cache consistency
and this can be satisfied by causal consistency.
ATOMIC stuff is where cores starts to require SC,
and all MMI/O should be SC or SC per virtual channel.