Re: PCIe MSI-X interrupts

On page 43 of::
https://www.cs.uml.edu/~bill/cs520/slides_15E_PCI_Express_IOV.pdf
it states: "Must not indicate an invalidation has completed
until all outstanding Read Requests that reference the
associated translation have retired"
"Must insure that the invalidation completion indication to RC
will arrive at the RC after previously posted writes that use
the stale address."
and
"...If transactions are in a queue waiting to be sent, It is
not necessary for the device to expunge requests from the
queue even if those transaction[s] use an address that is
being invalidated."
The first 2 seem to be PCIe ordering requirements between
EP and RC.
The 3rd seems to say if EP used a translation while it was
valid, then its invalidation does not prevent requests
using the now stale translation.
So, a SATA device could receive a command to read a page
into memory. SATA EP requests ATS for the translation of
the given virtual address to the physical page. Then the
EP creates a queue of write requests filling in the addr
while waiting on data. Once said queue has been filled,
and before the data comes off the disk, an invalidation
arrives and is ACKed. The data is still allowed to write
into memory.
{{But any new command to the SATA device would not be
allowed to use the translation.}}
Is this a reasonable interpretation of that page?