Re: Continuations

MitchAlsup1 <mitchalsup@aol.com> schrieb:

On Wed, 17 Jul 2024 18:30:47 +0000, Stephen Fuld wrote:
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MitchAlsup1 wrote:
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On Wed, 17 Jul 2024 16:50:27 +0000, Thomas Koenig wrote:
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MitchAlsup1 <mitchalsup@aol.com> schrieb:
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What I am talking about is to improve their performance until a
sin() takes about the same number of cycles of FDIV, not 10× more.

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Maybe time for a little story.
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Some unspecified time ago, a colleague did CFD calculations which
included fluid flow (including turbulence modelling and diffusion)
and quite a few chemical reactions together.  So, he evaluated a
huge number of Arrhenius equations,
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k = A * exp(-E_a/(R*T))
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and because some of the reactions he looked at were highly
exothermic or endothermic, he needed tiny relaxation factors (aka
small steps).  His calculaiton spent most of the time evaluating
the Arrhenius equation above many, many, many, many times.
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A single calculation took months, and he didn't use weak hardware.
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A fully pipelined evaluation of, let's say, four parallel exp and
four parallel fdiv instructions would have reduced his calculation
time by orders of magnitude, and allowed him to explore the design
space instead of just scratching the surface.
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(By the way, if I had found a reasonable way to incorporate the
Arrhenius equation into your ISA, I would have done so already :-)

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    FMUL     Rt,RR,RT
    FDIV     Rt,-RE,Rt
    EXP      Rt,Rt
    FMUL     Rk,RA,Rt
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Does not look "all that bad" to me.

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So for your GbOoO CPU, how many of the various FP operations, and the
EXP instruction can be done in parallel?

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FMUL is   4 cycles of latency fully pipelined
FDIV is ~20 cycles of latency not   pipelined
EXP  is ~16 cycles of latency not   pipelined

Ah, OK.

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They are all performed in the FMAC unit and here the instructions are
serially dependent.

A loop containing the calculation could be unrolled, but without
a large effect.

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So, 44 cycles of latency, a 1-wide machine and a 6-wide machine would
see the same latency; that is, GBOoO is not a differentiator.

What about SIMD width underlying the the VVM implementation?
All SIMD implementations I know of allow performing floating point
ops in paralell.  Is it planned that My 66000 can also do that?
(If not, that would be a big disadvantage for scientific/technical
work).