Re: Continuations

MitchAlsup1 wrote:

On Thu, 18 Jul 2024 0:48:18 +0000, EricP wrote:
 

MitchAlsup1 wrote:

 
{Would be an interesting reservation station design, though}

 
In what way would the RS be interesting or different?

 
The instruction stream consists of 4 FMAC-bound instructions unrolled
as many times as will fit in register file.
 
You typical reservation station can accept 1 new instruction per cycle
from the decoder. So, either the decoder has to spew the instructions
across the stations (and remember they are data dependent) or the
station has to fire more than one per cycle to the FMAC units.
 
So, instead of 1-in, 1-out per cycle, you need 4-in 4-out per cycle
and maybe some kind of exotic routing.

Please bear in mind that I am a big fan of VVM over SIMD instructions.
But . . . is this a potential drawback of VVM versus SIMD?  i.e.  that
as the number of execution units increases, the design of the
reservation sations gets more complex for VVM, but not for SIMD.  i.e.
It sounds like a CPU with 8 FMAC units would be a more difficult design
for VVM.

Is that an issue?





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 - Stephen Fuld
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