Sujet : Re: Continuations
De : tkoenig (at) *nospam* netcologne.de (Thomas Koenig)
Groupes : comp.archDate : 20. Jul 2024, 09:45:13
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <v7ftep$3fa1q$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
User-Agent : slrn/1.0.3 (Linux)
MitchAlsup1 <
mitchalsup@aol.com> schrieb:
On Thu, 18 Jul 2024 15:35:50 +0000, Thomas Koenig wrote:
>
Michael S <already5chosen@yahoo.com> schrieb:
On Thu, 18 Jul 2024 13:58:37 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:
>
Michael S <already5chosen@yahoo.com> writes:
On Thu, 18 Jul 2024 06:00:46 -0000 (UTC)
Thomas Koenig <tkoenig@netcologne.de> wrote:
>
>
>
What about SIMD width underlying the the VVM implementation?
All SIMD implementations I know of allow performing floating point
ops in paralell. Is it planned that My 66000 can also do that?
(If not, that would be a big disadvantage for scientific/technical
work).
>
All pre-Merom implementation of SSE2, i.e. Intel Pentium 4, Intel
Pentium-M and AMD K8, do not perform double precision floating point
>
>
All of which have been obsolete for almost two decades.
>
According to my understanding, Thomas Koenig was/is around for more
than three decades.
>
I have been (starting doing things on mainframes in the late 1980s),
but I was specifically asking about what Mitch had in mind for
My 66000.
>
I have a spectrum in mind; everything from an in order 1-wide to (as of
now) 6-wide GBOoO design with 4 FMAC units.
If you're thinking about 64-bit FMA units, that would
be half of what Intel apparently plans to put into their
"economy" cores with Skymont, which is four 128-bit FMA units:
https://chipsandcheese.com/2024/06/15/intel-details-skymont/
Continuations
Re: Continuations