Re: Chipsandcheese article on the CDC6600

On Mon, 22 Jul 2024 15:10:50 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:

 
IA-64 had 2× the number of pins compared to its x86 brethren.
No wonder it could consume more BW.

Madison Itanium with 400 MHz FSB had the same theoretical memory
bandwidth (6.4 GB/s) as AMD S939/S940 K8 Opteron/Athlon64 processors.
And somewhat lower practical bandwidth because of higher latency caused
by off-chip memory controller.
Despite that its SPECfp2000  scores were slightly (5-6%) higher.

Contemporary Intel x86 processors (Nocona Xeon) had twice narrower
data bus, but it was running at twice higher data rate. So, at least
theoretically, peak bandwidth was the same. Practically, bandwidth was
somewhat lower because source-synchronous bus of Xeon had higher
latency than simpler clock-synchronous bus of Itanium2.