Memory ordering (was: Arguments for a sane ISA 6-years later)

"Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:

On 7/26/2024 10:00 AM, Anton Ertl wrote:

"Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:

[...]

By contrast, one can design hardware for strong ordering such that the
slowness occurs only in those cases when actual (not potential)
communication between the cores happens, i.e., much less frequently.
 

and sometimes use cases do not care if they encounter "stale" data.

 
Great.  Unless these "sometimes" cases are more often than the cases
where you perform some atomic operation or barrier because of
potential, but not actual communication between cores, the weak model
is still slower than a well-implemented strong model.

>
A strong model? You mean I don't have to use any memory barriers at all?

In the paragraph above I had a weaker model and a stronger model in
mind, where the stronger model needs fewer barriers and atomic
operations than the weak model.

But sure, sequential consistency does not require any memory barriers,
so that would be the ultimate strong model, and, if implemented
efficiently, would beat the weaker TSO, just as an efficiently
implemented TSO beats weaker models.

Tell that to SPARC in RMO mode...

What about it?  If you mean that SPARC in TSO mode is slower, that may
be the case.  That's why I specified "well-implemented" above.

Even the x86 requires a
membar when a store followed by a load to another location shall be
respected wrt order.

So "the x86" (whatever you mean by that) is not sequentially
consistent.

I
thought it was easier for a HW guy to implement weak consistency? At the
cost of the increased complexity wrt programming the sucker! ;^)

Yes, that's why the hardware people love to give us weak consistency.
It's our job to say no and tell them to finish the job.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>