Re: YASV (Yet Another Security Vulnearability)

On Mon, 29 Jul 2024 21:25:11 +0000, EricP wrote:

MitchAlsup1 wrote:

On Sat, 27 Jul 2024 19:31:39 +0000, EricP wrote:
>
I am sitting around wondering if ASID might be used to avoid resetting
the predictors. If( myASID != storedASID ) don't use prediction.
This avoids the need to set 32KB of 4-state predictors to weakly
untaken. And then store 1 ASID per 512-bits of predictors, for a
3% overhead. Mc 68030 TLB did something like this.

>
If the (12 bit?) ASID is for 512 bit blocks then the overhead could
be acceptable. But some of these BP structures, BTB, are set assoc.
and would require a sequential scan to reset the entries for an ASID.

ASID = 16-bits (in my context)
When the BP is set associative, each group of 512-bits is accompanied by
a 16-bit ASID. If your access hits on a particular set, then you use
my ASID = storedASID as the discriminator.

It also depends on how quickly in the pipeline the mispredict can be
detected, some can be detected at Decode and others not until execute,
and how quickly unnecessary pending loads can be canceled and the
correct flow reestablished.

>
The mispredict logic also needs to be able to abort an I-TLB table walk
if BP erroneously tells Fetch to follow the wrong path.

Just like throwing away anything dumped into the pipeline.

Its probably not possible to abort an I$L1 cache miss as a miss buffer
would already be allocated for it. But I would not want the I$L1 cache
port to be tied up waiting for an unneeded prefetch read.

You might not be able to prevent the fetch of data, and you have
allocated
a Miss Buffer entry. But when the data arrives and you no longer need
it,
you are not (post Spectré) allowed to put it in the Icache, so the miss
buffer return it to main memory (dirty) or drops it (shared).