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mitchalsup@aol.com (MitchAlsup1) writes:Fair enough. But after thinking abut this for a while, does theOn Thu, 1 Aug 2024 20:34:28 +0000, Scott Lurndal wrote:>
>
>>>In addition, ARM64 CPUs include allocation hints in>
the memory type such as 'read allocate', 'transient read allocate',
'write allocate' as well has having optionally multiple coherency
domains (inner and outer sharable).
Sorry, I don't understand the word 'allocate' ?!?
"allocate a cache line".
>
Example would be a DMA request with the 'read allocate' hint
is allowed to be allocated in LLC instead of being stored in
DRAM.
>
Used when software expects the DMA data to be immediately.
Thanks for the explanation.
>
In my case LLC is simply the front end for DRAM so a device
write will spew data into LLC where it will wait to be written.
I'm not sure that's a good idea. Large DMAs are common
(e.g. reading pages of data in a single I/O) and the data
from the DMA is not always used by the CPU. Evicting LLC lines to
accomodate a file copy, for example, seems less than optimal.
>Yes, but the interconnect is designed to move large chunksWhen using memove() or memset() data is moved on page sized>
boundaries over the "bus".
IME the majority of memset calls are for relatively small
(less than a page) regions.
Les messages affichés proviennent d'usenet.