Re: My 66000 and High word facility

On Sat, 10 Aug 2024 18:17:54 +0000, Brett wrote:

>
My 66000 should look into the z/architecture High Word Facility as that
would give you another 65% more registers or so. You have the opcode
space and it is Another nice boost for some customers.

The article posted by Andy Glew was luke-warm at best. Now, while
IBM has figured out that 16 GPRs is insufficient, there is scant
data that 32 are insufficient {witness how few RISCs went with
bigger files}
Since My 66000 is a 64-bit architecture with a modicum of support for
8-bit, 16-bit, and 32-bit stuff; and since 32-truely GPRs seems to be
enough (compiler output), I think I will pass.
Due to significant access to constants, My 66000 with only 32-actual
registers performs as well as RISC-V does with 32I+32F in most codes,
so there does not seem to be an insufficient number of registers. I
even have ASM examples where RISC-V runs out of registers where My
66000 does not !! Not wasting register to hold onto big immediates,
big displacements, or big addresses goes a long way to thinning out
the register count necessities.
In My 66000 one can utilize all 32 registers, with 0 reserved for
{linking, splicing, GOT access,...} these "effective constants"
become actual constants meaning one does not have to consume a
register to have access through that constant address value.

IBM supports Linux, so the compiler support should exist. X86 solved the
aliasing issue with finer tracking.

Neither of which would worry me.

>
Thanks,
Brett