Re: Instruction Tracing

On Sat, 10 Aug 2024 21:34:47 +0000, BGB wrote:

>
My rough ranking of instruction probabilities (descending probability,
*):
   Load/Store (Constant Displacement, ~30%);
   Branch (~ 14% of ops);
   ALU, ADD/SUB/AND/OR (~ 13%);
   Load/Store (Register Indexed, ~10%);
   Compare and Test (~ 6%);
   Integer Shift (~ 4%);
   Register Move (~ 3%);
   Sign/Zero Extension (~ 3%);
   ALU, XOR (~ 2%);
   Multiply (~ 2%);
   ...
>
*: Crude estimate based on categorizing the dynamic execution
probabilities (which are per-instruction rather than by category).
>
Meanwhile, DIV and friends are generally closer to 0.05% or so...
   You can leave them out and hardly anyone will notice.

The literature from the CRAY-1 era indicated big number crunching
applications use FFDIV about ¼ that of FMUL, IDIV not so much.

>
For the most part, something like RISC-V makes sense, except that
omitting Indexed Load/Store is basically akin to shooting oneself in the
foot (and does result in a significant increase in the amount of Shift
and ADD instructions used).
>
>
With RISC-V, one may see ~ 25% Load/Store followed by ~ 20% ADD and 15%
Shift, ...

If you add the number of indexed LD/STs in your list above with shifts,
you can find all those missing RISC-V shift instructions.

Some of this is because ADD and Shift end up over-represented by their
need to be used in compound operations (indexed load/store and sign/zero
extension).

RISC-V 16-bit smash::
          SLI     Rt,Rs,48
          SRA     Rt,Rt,48
My 66000
          SLA     Rt,Rs,<16:0>
Where RISC-V uses the shifter at 48-bits twice, My 66000 only uses
the masking part of the shifter.
<snip>

>
Meanwhile, I am once again reminded of an annoying edge case bug in my
Verilog implementation:
If a TLB Miss happens on an inter-ISA branch, it can leave the CPU core
in an inconsistent state.

Woops...