Re: Instruction Tracing

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Sun, 11 Aug 2024 14:44:38 GMT, Anton Ertl wrote:
>

Power (IIRC) and Alpha don't have delayed branches.

>
Not only does POWER not have delayed branches, but I recall the IBM folks
claiming in the initial publicity that branches could often execute in
zero clock cycles--that is, fully overlapped with surrounding
instructions.

Yes.  Power has a sophisticated branch unit for its time.

POWER was also "superscalar" (being able to execute more than one
operation per clock cycle) right from the beginning. Not sure if other
RISC architectures of the time were like that. I don’t think Alpha was:
one thing I remember from its early descriptions was its use of very high
clock speeds.

Already the 21064 is two-wide superscalar (1 integer unit, 1 FPU, 1
load/store unit, don't remember if the branch unit could run in
parallel to the ALU; I think not).  And it has very high clock speeds
for its time; it appeared with 150MHz while the competition was like
50MHz (SuperSPARC, superscalar) to 100MHz (MIPS R4000, not
superscalar), or, for Power, 62.5MHz in the POWER1++.  But POWER1
(without ++) preceded the 21064 by 2 years.

That seemed to me to be the opposite of "(at least) one
instruction per clock cycle", which I thought was supposed to be one of
the defining features of RISC.

A peak (i.e., guaranteed not to be exceeded) performance of 1 IPC was
a goal in early RISCs.  I guess you could construct a program that has
1 IPC on the MIPS R2000 and the first SPARC, but for useful code the
IPC on these early RISC's is lower.  Likewise for the 21064, the peak
performance is 2 IPC, but performance on useful code is usually lower.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>