Re: Instruction Tracing

On Mon, 12 Aug 2024 15:14:53 +0000, Michael S wrote:

On Mon, 12 Aug 2024 08:42:51 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
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On Mon, 12 Aug 2024 11:09:18 +0300, Michael S wrote:
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On Mon, 12 Aug 2024 06:33:17 -0000 (UTC)
Lawrence D'Oliveiro <ldo@nz.invalid> wrote:
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But in spite of having, say, 2½ times the clock speed of POWER,
Alpha was not 2½ times faster, was it?

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Of course not.

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That’s what I mean: it took several clock cycles per instruction,
contrary to just about every other RISC architecture.

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On EV4 simple ALU instructions took 1 cycle , both for throughput and
for latency.
Shifts and conditional moves had latency of 2, throughput of 1.
Integer multiplier was not pipelined, but few RISC also had it
none-pipelined.

Mc88100 had a pipelined multiplier, you could start a int mul
every cycle or a single mul evey cycle or a double mul every 4
cycles.

                 Latency of integer multiplier was 19-21 cycles.

3 cycles for Mc88100

On FP side both FADD and FMUL were fully pipelined (T=1) and had
latency of 6 cycles.
L1D cache hits were fully pipelined (T=1) and had latency of 3 cycles.
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So, as long as code/data was fitting in L1 cache, EV4 IPC was not
far behind competition. Relatively to MIPS R4K, may be, even ahead.
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Of course, cache misses were relatively more expensive than for much
lower clocked competitors. DEC's solution to that was wide and fast
system bus.