Re: My 66000 and High word facility

On Sun, 11 Aug 2024 14:33:33 +0000, Anton Ertl wrote:

Brett <ggtgp@yahoo.com> writes:

The lack of CPU’s with 64 registers is what makes for a market, that 4%
that could benefit have no options to pick from.

>
They had:
>
SPARC: Ok, only 32 GPRs available at a time, but more in hardware
through the Window mechanism.

SPARCs FPGA through UltraSPARC used 1 full cycle to access the windowed
register file will MIPS, 88K, and early Alphas used 1/2 cycle. So SPARC
architecture saddled them with an inherent disadvantage....

AMD29K: IIRC a 128-register stack and 64 additional registers

Similar issues.

IA-64: 128 GPRs and 128 FPRs with register stack and rotating register
files to make good use of them.

Don't know for certain, but I would expect the same as above.

The additional registers obviously did not give these architectures a
decisive advantage.

Captain Obvious strikes again
Oh, and BTW, that 1/2 cycle of delay getting started should have cost
~5% IPC. But SAPRC never achieved high clock frequencies nor dis IA-64.

When ARM designed A64, when the RISC-V people designed RISC-V, and
when Intel designed APX, each of them had the opportinity to go for 64
GPRs, but they decided not to.  Apparently the benefits do not
outweigh the disadvantages.
>
Where is your 4% number coming from?
>
- anton