Re: My 66000 and High word facility

Brett <ggtgp@yahoo.com> wrote:

MitchAlsup1 <mitchalsup@aol.com> wrote:

On Mon, 12 Aug 2024 2:23:00 +0000, Brett wrote:
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BGB <cr88192@gmail.com> wrote:

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Another benefit of 64 registers is more inlining removing calls.
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A call can cause a significant amount of garbage code all around that
call,
as it splits your function and burns registers that would otherwise get
used.

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What I see around calls is MOV instructions grabbing arguments from the
preserved registers and putting return values in to the proper preserved
register. Inlining does get rid of these MOVs, but what else ??

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For middling functions, I spent my time optimizing heavy code, the 10% that
matters.
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The first half of a big function will have some state that has to be
reloaded after a call, or worse yet saved and reloaded.
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Inlining is limited by register count, with twice the registers the
compiler will generate far larger leaf calls with less call depth. Which
removes more of those MOVs.
>

I can understand the reluctance to go to 6 bit register specifiers, it
burns up your opcode space and makes encoding everything more difficult.

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I am on record as stating the proper number of bits in an instruction-
specifier is 34-bits. This is after designing Mc88K ISA, doing 3
generations
of SPARC chips, 7 years of x86-64, and Samsung GPU (and my own efforts)
Making the registers 6-bits would increase that count to 36-bits.

 My 66000 hurts less with 6-bits as more constants bits get moved to
extension words, which is almost free by most metrics.
 Only My 66000 can reasonably be able to implement 6-bits register
specifiers.
The market is yours for the taking.
 6-bits will make you stand out and get noticed.
 The only down side I see is a few percent in code density.