Re: Instruction counts (was: Decrement And Branch)

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Fri, 16 Aug 2024 05:23:30 GMT, Anton Ertl wrote:
>

... instruction count was not
among the criteria that John Mashey identified as discerning between
RISC and non-RISC (not surprising given non-RISCs like PDP-11).

>
Why is that particular criterion, of all of them, in the name, then?

It is not.  It's not Reduced InstructionS Computer, but "Reduced
Instruction Set Computer", and Mashey argued convincingly that this
should be read as "reduced-instruction set computer", not as "reduced
instruction-set computer".

If it was "reduced instruction-set computer", then the RISCs should
have kept the VAX shift instruction, which shifted in either
direction, depending on the sign of the shift count.  Instead, RISCs
generally split this instruction into a shift-left and shift-right
instruction, increasing the instruction count.

At one point I thought it should be “IRSC”, for “Increased Register Set
Computer” ...

This is one commonality of RISCs, but does not discern between RISCs
like the original IBM 801 (16 registers) and ARM A32 on one hand, and
S/360, VAX and AMD64 on the other hand (and especially not AMD64 with
APX).  In any case, number of registers certainly is one of the
criteria that John Mashey uses, but he uses a number of criteria, and
these work well for classifying architectures that he did not classify
in his original postings
<2024Jan12.145502@mips.complang.tuwien.ac.at>.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>