Re: number of registers

anton@mips.complang.tuwien.ac.at (Anton Ertl) writes:

mitchalsup@aol.com (MitchAlsup1) writes:

The point is that the cost of not getting allocated into a register
is vastly lower--the count of instructions remains 1 while the
latency increases. That increase in latency does not hurt those
use once/seldom variables.

>
Latency is not the issue in modern high-performance AMD64 cores, which
have zero-cycle store-to-load forwarding
<http://www.complang.tuwien.ac.at/anton/memdep/>.
>
And yet, putting variables in registers gives a significant speedup:
On a Rocket Lake, numbers are times in seconds:
>
sieve bubble matrix   fib   fft
0.075  0.070  0.036 0.049 0.017 TOS in reg, RP in reg, IP in reg
0.100  0.149  0.054 0.106 0.037 TOS in mem, RP in mem, IP write-through to mem
>
In the first line, I used gforth-fast and tried to disable all
optimizations except those that keep certain variables in registers:
>
gforth-fast --ss-states=1 --ss-number=31 --opt-ip-updates=0 onebench.fs
>
I could not reduce the static superinstructions below 31 and still get
a result; I will have to investigate why, but that probably does not
make that much of a difference for several of these benchmarks.

Fixed that, so now with

gforth-fast --ss-states=1 --ss-number=0 --opt-ip-updates=0 onebench.fs

sieve bubble matrix   fib   fft
0.069  0.074  0.036 0.052 0.017 TOS in reg, RP in reg, IP in reg
0.100  0.149  0.054 0.106 0.037 TOS in mem, RP in mem, IP write-through to mem

Or on a Golden Cove:

 sieve bubble matrix   fib   fft
 0.059  0.059  0.024 0.047 0.020 TOS in reg, RP in reg, IP in reg
 0.108  0.156  0.065 0.098 0.037 TOS in mem, RP in mem, IP write-through to mem

So even on these advanced cores with zero-cycle store-to-load
forwarding it hurts quite a bit to keep variables in memory.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>