Re: Banked register files

The old DEC/Intel, later Netronome, IXP network processors had two banks of
128 registers each, with the source operands had to come from different
banks.  Funky machine, lots of visible pipeline delays.  Limited scratch
memory with 3-cycle latency and explicit address register.  DRAM was an I/o
device with asynchronous load/store.

Not for C programmers. An optimizing assembler handled register assignment
and filled pipeline delay slots