Re: Banked register files

On Mon, 26 Aug 2024 21:10:48 +0000, Brett wrote:

Brett <ggtgp@yahoo.com> wrote:

Robert Finch <robfi680@gmail.com> wrote:

On 2024-08-22 5:58 p.m., Brett wrote:

Brett <ggtgp@yahoo.com> wrote:

MitchAlsup1 <mitchalsup@aol.com> wrote:

>
I saw a design where there was an attempt to process basic blocks in
parallel silos feeding functional units. It made use of fewer registers
by holding data in pipeline registers instead of GPRs which it could do
since some of the data for a basic block never goes outside the block.

>
No reply’s, so I figure y’all are under NDA. ;)

It has been well known since mid 1990s that most loops end up with a
single
or dual stream of self dependent instructions and few loop dependencies
{mostly the loop index itself}. This leads to instruction dependency
graphs (and execution times) that look like::
     | LD  |
     | LD  |
           |    FMUL    |
                        |    FADD    |
     | STA |                         | STD |
     | ADD |
           | CMP |
                 | BV  |
------------------------------------------------------------
           | LD  |
           | LD  |
                 |    FMUL   |