Re: Computer architects leaving Intel...

scott@slp53.sl.home (Scott Lurndal) writes:

Thomas Koenig <tkoenig@netcologne.de> writes:

Scott Lurndal <scott@slp53.sl.home> schrieb:
>

The problem with this is that RISC-V isn't currently comparable,
feature-wise, with ARMv8.0.    To compete with Neoverse-N2 cores,
they'll need to support a similar feature set - most of which doesn't
exist in the RISC-V design space yet.

>
What is missing (in broad terms)?

>
NeoverseN3 is ARMv9.2.   The list of ISA features from V8.0 to v9.2 is
quit extensive.

I think the lack of "extensive" features is a feature of RISC-V.  Last
I heard, the ARM manual was >10000 pages.

The RISC-V user manual has put on a lot of weight since Volume I
(unpriviledged) Version 2.2 (145 pages) and Volume II (priviledged)
20211203 (155 pages).  The 20240411 draft of Volume I weighs in at 670
pages), and the 20240411 draft of Volume II at 172 pages, but that's
still quite a long way from 10000.

One interesting case here is that the 236-page version
20190608-Base-Ratified of Volume I spends 12 pages on Chapter 14
"RVWMO Memory Consistency Model, Version 0.1" plus 30 pages for
"Appendix A RVWMO Explanatory Material, Version 0.1" plus 27 pages on
"Appendix B Formal Memory Model Specifications, Version 0.1"
(apparently not grown further in 20240411; the number of pages is a
little smaller for each of the parts).

If the goal of RISC-V was a really simple ISA (as in "simple to
specify"), they would have gone for sequential consistency, but
obviously the lure of implementation simplicity won out here.

Many of them are related to supporting server-grade
RAS, Memory Partitioning, address translation (e.g. 52-bit PA, 52-bit VA)
or accelerator interfaces (ST64B, LD64B).

Can't say I ever missed such instructions.

Are RAS instructions like memory-ordering instructions?  The hardware
does not provide the feature, but it provides instructions for
throwing the problem over to software, which is then supposed to use
those instructions (but not too often) to provide the feature that
hardware does not provide?

Moreover, they have a mature SoC ecosystem

ARM certainly has that.  However, a lot of the SoC ecosystem is only
accessed through drivers that are specific to one kernel and that
nobody maintains, and that's why many smartphones don't get any
updates after a few years.  Let's hope it's better for servers.

One hope is that the openness of RISC-V will also create a more open
ecosystem that will result in drivers in mainline Linux.  But my guess
is that for smartphones, the economic incentives are in the other
direction.   For servers things may be better, though (even on ARM).

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>