Re: Computer architects leaving Intel...

On Thu, 29 Aug 2024 3:36:44 +0000, BGB wrote:

On 8/28/2024 11:40 AM, MitchAlsup1 wrote:

On Wed, 28 Aug 2024 3:33:40 +0000, BGB wrote:

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And what kind of code compatibility would you have between different
designs...
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If people can agree as to the encodings, then implementations are more
free to pick which extensions they want or don't want.
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If the encodings conflict with each other, no such free choice is
possible.

With differing instructions, how does a software vendor write software
such that it can run near optimally on any implementation ??

Prolog/Epilog happens once per function, and often may be skipped for
small leaf functions, so seems like a lower priority. More so, if one
lacks a good way to optimize it much beyond the sequence of load/store
ops which is would be replacing (and maybe not a way to do it much
faster than however can be moved in a single clock cycle with the
available register ports).

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My 1-wide machines does ENTER and EXIT at 4 registers per cycle.
Try doing 4 LDs or 4 STs per cycle on a 1-wide machine.

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It likely isn't going to happen because a 1-wide machine isn't going to
have the needed register ports.

3R1W most of the time converts to 4R or 4W for the *logues.

But, if one doesn't have the register ports, there is likely no viable
way to move 4 registers/cycle to/from memory (and it wouldn't make sense
for the register file to have a path to memory that is wider than what
the pipeline has).

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This is likely the fate of nearly every hobby class ISA.
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Time to up your game to an industrial quality ISA.

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Open question of what an "industrial quality" ISA has that BJX2 lacks...
   Limiting the scope to things that RISC-V and ARM have.

Proper handling of exceptions (ignoring them is not proper)
Proper IEEE 754-2018 handling of FMAC (compute all the  bits)
Floating Point Transcendentals
HyperVisors/Secure Monitors
Write Interrupt service routines entirely in HLL
proper Privileges and Priorities
Multi-location ATOMIC events
..

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