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ENTER, LEAVE, and RET as the only instructions capable of accessing thea) I did not want to consume another bit in PTE
safe stack is fascinating me. I would like to try implementing this sort
of thing in my design. Pondering why the PTE is specially marked
RWE=000? One would think that some other OS available bits could be
used. Does it make the MMU software easier to implement? Assuming that
faults processed during ENTER, LEAVE, and RET are processed at a higher
privilege level, could it not just check some other internal tables?
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Decided to try implementing a capabilities machine in the current
design. Modeled it after the RISC-V capabilities instructions in the
CHERI document. It was either that or a segmentation system. Got to keep
the ole brain working.
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Going with an OoO design for Bigfoot.
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The rf386 takes an average of about 8 clocks per instruction. Helped out
by the presence of a data cache. IPC of 0.125 is nothing to write about.
About 5 MIPs at 50 MHz. Stores are fast (2-3 cycles), but loads are
another story (14 ish cycles).
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