Re: arm ldxr/stxr vs cas

On 9/4/2024 2:27 PM, MitchAlsup1 wrote:

On Mon, 2 Sep 2024 17:27:57 +0000, jseigh wrote:
 

I read that arm added the cas instruction because they didn't think
ldxr/stxr would scale well.  It wasn't clear to me as to why that
would be the case.  I would think the memory lock mechanism would
have really low overhead vs cas having to do an interlocked load
and store.  Unless maybe the memory lock size might be large
enough to cause false sharing issues.  Any ideas?

 A pipeline lock between the LD part of a CAS and the ST part of a
CAS is essentially FREE. But the same is true for LL followed by
a later SC.

100% sure on that? No way to break the reservation from an unrelated aspect wrt LL/SC?

 Older machines with looser than sequential consistency memory models
and running OoO have a myriad of problems with LL - SC. This is
why My 66000 architecture switches from causal consistency to
sequential consistency when it encounters <effectively> LL and
switches bac after seeing SC.
 No Fences necessary with causal consistency.
 

Joe Seigh