Sujet : Re: arm ldxr/stxr vs cas
De : mitchalsup (at) *nospam* aol.com (MitchAlsup1)
Groupes : comp.archDate : 08. Sep 2024, 01:59:51
Autres entêtes
Organisation : Rocksolid Light
Message-ID : <7ca6928a45e4cae89ba50a4623809d1c@www.novabbs.org>
References : 1 2 3 4 5 6 7 8 9 10 11 12
User-Agent : Rocksolid Light
On Sat, 7 Sep 2024 23:16:35 +0000, Chris M. Thomasson wrote:
On 9/7/2024 4:14 PM, Chris M. Thomasson wrote:
[...]
When I am using CAS I don't really expect it to fail willy nilly even if
the comparands are still the same. Weak vs Strong. Still irks me a bit.
;^)
>
There are algorithms out there, usually state machines that depend on
strong cas. When a CAS fails, it depends on it failing because the
comparands were actually different...
Leading to ABA failures::
Do you really want the following CAS to succeed ??
LD R19,[someMemoryValue]
..
interrupt delays program execution for 1 week
..
CAS R17,R19,[someMemoryLocation]
Given that the someMemoryLocation is accessible to other programs
while tis one is sleeping ??
Thus, it seems reasonable to fail a CAS when one cannot determine
if the memory location has been changed and changed back in the
mean time.
arm ldxr/stxr vs cas
Re: arm ldxr/stxr vs cas