Sujet : Re: arm ldxr/stxr vs cas
De : chris.m.thomasson.1 (at) *nospam* gmail.com (Chris M. Thomasson)
Groupes : comp.archDate : 08. Sep 2024, 08:35:07
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vbjgiq$1rat4$1@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13
User-Agent : Mozilla Thunderbird
On 9/7/2024 5:59 PM, MitchAlsup1 wrote:
On Sat, 7 Sep 2024 23:16:35 +0000, Chris M. Thomasson wrote:
On 9/7/2024 4:14 PM, Chris M. Thomasson wrote:
[...]
When I am using CAS I don't really expect it to fail willy nilly even if
the comparands are still the same. Weak vs Strong. Still irks me a bit.
;^)
>
There are algorithms out there, usually state machines that depend on
strong cas. When a CAS fails, it depends on it failing because the
comparands were actually different...
Leading to ABA failures::
Do you really want the following CAS to succeed ??
LD R19,[someMemoryValue]
..
interrupt delays program execution for 1 week
..
CAS R17,R19,[someMemoryLocation]
Given that the someMemoryLocation is accessible to other programs
while tis one is sleeping ??
Thus, it seems reasonable to fail a CAS when one cannot determine
if the memory location has been changed and changed back in the
mean time.
ABA, well that can happen with CAS and certain algorithms that use them. The good ol' version counter is pretty nice, but it still can fail. 64 bit words, 128 bit CAS. Loads to boot... ;^) Actually, I think Joe mentioned something interesting about CAS a long time ago wrt IBM... Candy Cane Striped books (Joe do you remember?) about a way to avoid live lock and failing in the os. I think Windows has some like it with their SList and SEH?
arm ldxr/stxr vs cas
Re: arm ldxr/stxr vs cas