Sujet : Re: arm ldxr/stxr vs cas
De : chris.m.thomasson.1 (at) *nospam* gmail.com (Chris M. Thomasson)
Groupes : comp.archDate : 08. Sep 2024, 21:29:11
Autres entêtes
Organisation : A noiseless patient Spider
Message-ID : <vbl1en$22022$2@dont-email.me>
References : 1 2 3 4 5 6 7 8 9 10 11 12 13 14
User-Agent : Mozilla Thunderbird
On 9/8/2024 9:10 AM, Scott Lurndal wrote:
"Chris M. Thomasson" <chris.m.thomasson.1@gmail.com> writes:
On 9/7/2024 5:59 PM, MitchAlsup1 wrote:
On Sat, 7 Sep 2024 23:16:35 +0000, Chris M. Thomasson wrote:
Thus, it seems reasonable to fail a CAS when one cannot determine
if the memory location has been changed and changed back in the
mean time.
>
I think Scott Lurndal mentioned something about CAS or something on
windows that will assert the bus lock after a lot of failures...
On AMD processors (and likely intel), if a core cannot acquire
a cache line in a a finite time, the core will assert the bus lock
to ensure forward progress.
Nothing to do with the operating software; purely a hardware thing.
Ahhhh! Thanks for your clarification. :^)
arm ldxr/stxr vs cas
Re: arm ldxr/stxr vs cas