Re: is Vax addressing sane today

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

Perhaps there is also the issue of the wildly-variable instruction length.
A single VAX operand descriptor could be up to 6 bytes; I think the
instruction with the most general-format operands could have 6 of them:
so, plus opcode, such an instruction could be 37 bytes long.

The regularity of the VAX operand formats may actually help build the
decoder: Decode your byte stream as possible operands, and then let
the instruction decoder pick the real operands from the potential
operands.

Even those who are talking about “post-RISC” are, I think, still in favour
of RISC-style fixed instruction lengths.

Even among the RISCs, fixed instruction lengths are not universal: ARM
T32 has two widths, as has RV64GC (and RISC-V has provisions for
additional lengths, but AFAIK nobody uses them yet); there was also
ROMP and MIPS16.

Interestingly, despite their ample experience with T32, ARM went
fixed-length with A64, but then the market for A64 is probably not as
code-size sensitive as that for T32.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>