Re: is Vax addressing sane today

John Levine <johnl@taugh.com> writes:

According to Anton Ertl <anton@mips.complang.tuwien.ac.at>:

The regularity of the VAX operand formats may actually help build the
decoder: Decode your byte stream as possible operands, and then let
the instruction decoder pick the real operands from the potential
operands.

>
Urrgh. Some of those bogus operands are indirect indexed auto-increment, so you
are going to be throwing away a whole lot of work.

Yes, AFAIK that's how multi-instruction decoding for variable-width
instruction sets works these days: Decode at every potential
instruction start, then select those decoded instructions that are at
actual instruction boundaries, and throw the others away.

Compare that to zSeries, where even after 50 years of sticking new instructions
into the holes in the S/360 instruction set, it can still tell the length of the
instruction from the first two bits and the operands from the first byte.

Good for sequential decoding, and maybe it makes parallel decoding
cheaper (but OTOH, the first superscalar S/360 descendent came out in
2000, 7 years after the superscalar Pentium, and the first OoO S/360
descendent lagged the Pentium Pro by 14 years or so), but as the IIRC
6-wide decoder of Alder Lake demonstrates, hardware designers are able
to deal with instruction sets that do not have such nice properties:
an AMD64 instruction can have a large number of prefixes, and I think
that the encoding of indexed addressing is not announced in the first
non-prefix instruction byte, either.

- anton
--
'Anyone trying for "industrial quality" ISA should avoid undefined behavior.'
  Mitch Alsup, <c17fcd89-f024-40e7-a594-88a85ac10d20o@googlegroups.com>