Re: arm ldxr/stxr vs cas

I suspect at least theoretically conditions could exist where
having more than one lock within a cache line would be beneficial.
If lock B is always acquired after lock A, then sharing a cache
line might (I think) improve performance. One would lose

I suspect in practice this almost never happens because if it did, it
would mean that the program would benefit from merging those two locks
into a single one.


        Stefan