Re: Tonights Tradeoff

On 2024-09-12 4:21 a.m., BGB wrote:

On 9/12/2024 12:37 AM, Thomas Koenig wrote:

MitchAlsup1 <mitchalsup@aol.com> schrieb:

On Tue, 10 Sep 2024 7:00:00 +0000, BGB wrote:
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On 9/9/2024 10:59 PM, Robert Finch wrote:

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Still trying to grasp the virtual vector method. Been wondering if it
can be implemented using renamed registers.
>

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I haven't really understood how it could be implemented.
But, granted, my pipeline design is relatively simplistic, and my
priority had usually been trying to make a "fast but cheap and simple"
pipeline, rather than a "clever" pipeline.

>
"Good, Fast, Cheap; choose any 2" Lee Higbe 1982.

>
Still beeter than "Good, Fast, Cheap: Chose one."

 One can take note of all my corner-cutting...
 I was mostly trying to prioritize fast and cheap, but sadly it is neither as fast nor as cheap as I would want.
   Though, ironically, will put at least some of the cost blame on RISC-V, which doesn't go quite so hard on the corner cutting.
 But, one can maybe argue that it is a bit much to try to push for a 64- bit ISA that only natively has 32-bit integer multiply, ...
 Though, this is not to say that other possible implementations couldn't try to do everything "properly".
 

I am partial to good and fast myself. Spare no expense. Have to ensure that things are expensive enough, but no more expensive than needed.
Cost is always a factor.
There were case statements and shifters to handle applying a vector mask for different precisions. Too much logic. So, the case statements were eliminated, and the lowest common denominator used. Now, vector masking is applied only at the byte level. There is a mask bit for each byte of the vector register. To mask off a tetra-byte for instance, four consecutive mask bits must be cleared. I do not think this is a big deal as it is a matter of loading one constant or another into a mask register. A helper instruction to handle the masking could be added.