Re: Tonights Tradeoff

On Thu, 12 Sep 2024 3:37:22 +0000, Robert Finch wrote:

On 2024-09-11 11:48 a.m., Stephen Fuld wrote:

On 9/11/2024 6:54 AM, Robert Finch wrote:
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I have found that there can be a lot of registers available if they
are implemented in BRAMs. BRAMs have lots of depth compared to LUT
RAMs. BRAMs have a one cycle latency but that is just part of the
pipeline. In Q+ about 40k LUTs are being used just to keep track of
registers. (rename mappings and checkpoints).
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Given a lot of available registers I keep considering trying a VLIW
design similar to the Itanium, rotating register and all. But I have a
lot invested in OoO.
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Q+ has seven in-order pipeline stages before things get to the re-
order buffer.

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Does each of these take a clock cycle?  If so, that seems excessive.
What is your cost for a mis-predicted branch?
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Each stage takes one clock cycle. Unconditional branches are detected at
the second stage and taken then so they do not consume as many clocks.
There are two extra stages to handle vector instructions. Those two
stages could be removed if vectors are not needed.
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Mis-predicted branches are really expensive. They take about six clocks,
plus the seven clocks to refill the pipeline, so it is about 13 clocks.
Seems like it should be possible to reduce the number of clocks of
processing during the miss, but I have not got around to it yet. There
is a branch miss state machine that restores the checkpoint. Branches
need a lot of work yet.

In a machine I did in 1990-2 we would fetch down the alternate path
and put the recovery instructions in a buffer, so when a branch was
mispredicted, the instructions were already present.
So, you can't help the 6 cycles of branch verification latency,
but you can fix the pipeline refill latency.
We got 2.05 i/c on XLISP SPECnit 89 mostly because of the low backup
overhead.

I am not sure how well the branch prediction works. Instruction runs in
SIM are not long enough yet. Something in the AGEN/TLB/LSQ is not
working correctly yet, leading to bad memory cycles.