Re: arm ldxr/stxr vs cas

On 9/11/2024 7:33 AM, Stefan Monnier wrote:

I suspect at least theoretically conditions could exist where
having more than one lock within a cache line would be beneficial.
If lock B is always acquired after lock A, then sharing a cache
line might (I think) improve performance. One would lose

 I suspect in practice this almost never happens because if it did, it
would mean that the program would benefit from merging those two locks
into a single one.

Side note... Address based hash locking schemes can be used to emulate atomics in standard C++ when is_lock_free would be false. Here is one I did for fun:
https://en.cppreference.com/w/cpp/atomic/atomic/is_lock_free
It can merge locks into one wrt hash collisions, think of the hash algorithm. Sorting the locks and removing duplicates, taking the locks in order makes it deadlock free. Here is an example of such a locking scheme. I called it the multex:
https://groups.google.com/g/comp.lang.c++/c/sV4WC_cBb9Q/m/SkSqpSxGCAAJ
(read all when you get some time...)