Re: Is Intel exceptionally unsuccessful as an architecture designer?

On Wed, 18 Sep 2024 16:04:14 +0000, Michael S wrote:

On Wed, 18 Sep 2024 15:40:51 GMT
scott@slp53.sl.home (Scott Lurndal) wrote:
>

Lawrence D'Oliveiro <ldo@nz.invalid> writes:

On Tue, 17 Sep 2024 23:45:50 +0000, MitchAlsup1 wrote:
>

"the CPUs are simply I/O managers to the Inference Engines and
GPUs."

>
That particular Wheel of Reincarnation will never turn that way.

>
And, your lack of knowledge strikes again.   Such bespoke CPUs
are more and more common every month, with many currently
in tape-out or late-stage design by several fabless semiconductor
companies.
>

>
Why? It comes down to RAM. Those addon processors will never have
access to the sheer quantity of RAM that is available to the CPU.

>
That's also incorrect.   There is nothing preventing them from
accessing huge amounts of RAM when included on-die or via
chiplets.   Consider CXL-Cache, which provides high-bandwidth
low-latency access to huge amounts of DRAM.  Consider stacked
HBM.  Consider not drawing conclusions from insufficient knowledge.
>

>
Low latency?
I'd think that the latency here at very least 5x higher than 45-60ns
figures typical for Intel/AMD/Apple/Qualcomm client CPUs.
And I am afraid that 10x is more common than 5x.

2 points:
Yes: CXL-Cache and CXL memory have significantly more latency than
direct attach DAM DIMMs. With PCIe 6.0 this should be an adder
of 50-60 ns over the latency of the cache hierarchy on die. So,
yes it is slower than the kinds of caches we are used to, but
when compared to the latency of SSD and spinning rust it is
way better.
-----
On the other hand, and this is where the deprecation of the CPUs
come in, The engines consuming the data are bandwidth machines
{GPUs and Inference engines} which are quite insensitive to
latency (they are not not latency bound machines like CPUs).
When doing GPUs, a memory access taking 400 cycles would hardly
degrade the overall GPU performance--while it would KILL any
typical CPU architecture.