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EricP <ThatWouldBeTelling@thevillage.com> wrote:Terje Mathisen wrote:EricP wrote:
I always assumed that MULH just grabbed the part that would have beenIt is easy enough in the decoder to recognize a MUL followed by MULH
thrown away. And that is how at least one RISC-V core does it:
>
https://www.digikey.com/en/blog/how-the-risc-v-multiply-extension-adds-an-efficient-32-bit
>
They claim 5 cycles, should be six, five for the multiply and one more
for the second result, unless the next instruction does not need a write
port, and does not use the result. You can get a throughput of 5 cycles
with
smart coding, but that rarely happens without effort.
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