Re: Is Intel exceptionally unsuccessful as an architecture designer?

On 19/09/2024 18:09, MitchAlsup1 wrote:

On Thu, 19 Sep 2024 7:01:13 +0000, David Brown wrote:
 

On 19/09/2024 00:54, Lawrence D'Oliveiro wrote:

On Wed, 18 Sep 2024 16:23:01 +0000, MitchAlsup1 wrote:
>
But if it’s supposed to be for “interactive” use, it’s still going to
take
those 400 memory-cycle times to return a response.

>
In human terms, those 400 memory cycles are completely negligible.  For
most purposes, anything else than 100 milliseconds is an instant
response.  For high-speed games played by experts, 10 milliseconds is a
good target.  For the most demanding tasks, such as making music, 1
millisecond might be required.

 400 cycles IS negligible.
400 cycles for each LD is non-negligible.
 

Sure.
My understanding was that the extra cycles were latency on the handling of particular events or requests - after that, you had the data locally.   If you had that kind of delay individually for each load, then I completely agree it is far from negligible.

Remember LDs are 20%-22% of the instruction stream and with 400 cycles
per LD you see an average of 80-cycles per instruction even if all
other instructions take 1 cycle. This is 160× SLOWER than current
CPUs. But GPUs with thousands of cores can use memory that slow and
still deliver big gains in performance (6×-50×).
 

For anything interactive, an extra 400 memory cycles latency means
nothing - even if it is relatively slow memory - as long as you can keep
the throughput.  Network latency is massively bigger than this extra
memory latency would be.

 Most CPUs can't even deliver control in 400 cycles to an interrupt
or exception handler.