Re: Computer architects leaving Intel...

On Fri, 20 Sep 2024 0:12:48 +0000, Brett wrote:

MitchAlsup1 <mitchalsup@aol.com> wrote:

On Thu, 19 Sep 2024 19:12:41 +0000, Brett wrote:
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MitchAlsup1 <mitchalsup@aol.com> wrote:

On Thu, 19 Sep 2024 15:07:11 +0000, EricP wrote:

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- register specifier fields are either source or dest, never both

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I happen to be wishywashy on this

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This is deeply interesting, can you expound on why it is fine a register
field can be shared by loads and stores, and sometimes both like x86.

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My 66000 encodes store data register in the same field position as it
encodes "what kind of branch" is being performed, and the same position
as all calculation (and load) results.
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I started doing this in 1982 with Mc88100 ISA, and never found a problem
with the encoding nor in the decoding nor with the pipelining of it.
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Let me be clear, I do not support necessarily damaging a source operand
to fit in another destination as::
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    ADD     SP,SP,#0x40
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by specifying SP only once in the instruction.
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So,
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    +------+-----+-----+----------------+
    | major| Rd  | Rs1 | whatever       |
    +------+-----+-----+----------------+
    |  BC  | cnd | Rs1 | label  offset  |
    +------+-----+-----+----------------+
    |  LD  | Rd  | Rb  | displacement   |
    +------+-----+-----+----------------+
    | ST   | Rs0 | Rb  | displacement   |
    +------+-----+-----+----------------+
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Is:
a) no burden in encoding
b) no burden in decoding
c) no burden in pipelining
d) no burden in stealing the Store data port late in the pipeline
  {in particular, this saves lots of flip-flops deferring store
   data until after cache hit, TLB hit, and data has arrived at
   cache.}
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I disagree with things like::
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    +------+-----+-----+----------------+
    | big OpCode | Rds | whatever       |
    +------+-----+-----+----------------+
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Where Rds means the specifier is used as both a source and destination.
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Notice in my encoding one can ALWAYS take the register specification
fields and wire them directly into the RF/renamer decoder ports.
You lose this property the other way around.
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Classic RISC says the loads are critical, but no one is one wide today,

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SiFive disagrees with you.
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so
stores matter for deconfliction…. And does stuff just fall out right to
allow both?

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Can you restate what you wanted to say using different words or perhaps
give an example ??
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A series of adds to the same register in a four wide design.
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A = A + 1
A = A + B
A = A + C
A = A + D

Which any good compiler should emit as::
T1 = A + B
T2 = C + D
A  = LEA( T1, T2, #1 )
With a 2 cycle latency instead of 4.