Re: Computer architects leaving Intel...

On Fri, 20 Sep 2024 2:09:35 +0000, BGB wrote:

On 9/18/2024 1:42 PM, MitchAlsup1 wrote:
>
One simple option would be to assume an instruction looks like:
   [Prefix Bytes]
   [REX byte]
   OP_Byte | 0F+OP_Byte
   Mod/RM + SIB + ...

No, the simple option is that an instruction looks like:
     +------+-----+-----+----------------+
     | major| Rd  | Rs1 | imm16          |
     +------+-----+-----+----------------+
     | mem  | Rd  | Rb  | disp16         |
     +------+-----+-----+----------------+
     | Bcnd | cnd | Rs1 | disp18         |
     +------+-----+-----+----------------+
     | 2OP  | Rd  | Rs1 |mods| 2op | Rs2 |
     +------+-----+-----+----------------+
     | 3OP  | Rd  | Rs1 | Rs3 | 3op| Rs2 |
     +------+-----+-----+----------------+

And then use a heuristic to try to guess how to interpret the
instruction stream based on "looks better" (more likely to be aligned
with the instruction stream vs random unaligned garbage).
>
Though, such a "looks good" heuristic could itself risk skewing the
results.
>
>

I may still consider defining an encoding for this, but not yet. It is
in a similar boat as auto-increment. Both add resource cost with
relatively little benefit in terms of overall performance.
Auto-increment because if one has superscalar, the increment can usually
be co-executed. And, full [Rb+Ri*Sc+Disp], because it is just too
infrequent to really justify the extra cost of a 3-way adder even if
limited mostly to the low-order bits...

>
Myopathy--look it up.

>
>
OK.
>
Not sure how that is related (a medical condition involving muscle
defects...).

Myopathy is NEAR SIGHTEDNESS.
You are not looking far enough into the future to avoid problems in your
ISA and architecture. {I did the same in my youth. almost everyone
does.}

Can also note that a worthwhile design goal is to not add significant
cost over what would be needed for a plain RV64GC implementation, but,
could define a [Rb+Ri*Sc+Disp] encoding or similar if it would likely be
beneficial enough to justify its existence.

486 showed that "[Rbase+Rindex<<scale+displacement]:segment" could all
be performed in a single cycle at a frequency competitive with the RISC
processors available at the time.