Re: Is Intel exceptionally unsuccessful as an architecture designer?

On Mon, 23 Sep 2024 21:34:03 +0000, Michael S wrote:

On Mon, 23 Sep 2024 21:10:00 +0000
mitchalsup@aol.com (MitchAlsup1) wrote:
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On Mon, 23 Sep 2024 15:06:50 +0000, Scott Lurndal wrote:
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"Paul A. Clayton" <paaronclayton@gmail.com> writes:

On 9/17/24 8:44 PM, Lawrence D'Oliveiro wrote:

On Tue, 17 Sep 2024 23:45:50 +0000, MitchAlsup1 wrote:
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"the CPUs are simply I/O managers to the Inference Engines and
GPUs."

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That particular Wheel of Reincarnation will never turn that way.
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Why? It comes down to RAM. Those addon processors will never have
access to the sheer quantity of RAM that is available to the CPU.
And motherboard-based CPU RAM is upgradeable, as well, whereas
addon cards tend not to offer this option.

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My guess would be that CPU RAM will decrease in upgradability.

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LDO's statement "will never have access to the sheer quantity of
RAM that is available to the CPU" is flat out wrong.
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Marvell already offers a CXL add-on processor card that supports
up to 4TB of DRAM with 16 high-end ARM64 V series cores.

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At somewhere near 3× the latency to DRAM.
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Where did you find this figure?

I calculated it based on how messages get passed up and down PCIe
linkages and that that plug in memory has to be enough wire distance
to need a PCIe switch between CPU die and Plug. Then add on typical
memory controller and DRAM controller, and that is what you have.

I have read both product brief and press release and didn't see any
latency numbers mentioned, not even an order of magnitude.
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I suppose, in order to get real datasheet one would have to sign NDA.
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Somehow I don't see how anything running over PCIe-like link can be
as fast as you suggest.

I was not suggesting it is fast, I was suggesting it is slow.

If the size works for your application--great !
If the latency does not work for you--less great.