Re: Is Intel exceptionally unsuccessful as an architecture designer?

On 9/23/2024 3:32 PM, MitchAlsup1 wrote:

On Mon, 23 Sep 2024 22:19:37 +0000, Chris M. Thomasson wrote:
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On 9/23/2024 2:58 PM, MitchAlsup1 wrote:

On Mon, 23 Sep 2024 21:35:53 +0000, Chris M. Thomasson wrote:

Iirc, been a while, I think there was a problem on one of the Pentiums,
might be the pro, where it had an issue with releasing a spinlock with a
normal store. I am most likely misremembering, but it is sparking some
strange memories. Way back on c.p.t, Alex Terekhov (hope I did not
butcher the spelling of his name), anyway, wrote about it, I think...
Way back. early 2000's I think.

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Many ATOMIC sequences start or end without any note on the memory
reference that it bounds an ATOMIC event. CAS has this problem
on the value to ultimately be compared (the start), T&S has this
problem on ST that unlocks the lock (the end). It is like using
indentation as the only means of signaling block structure in
your language of choice.

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_Strong_ CAS in C++ terms, ala cmpxchg, will only fail if the comparands
are different.

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And used improperly is subject to ABA problem.
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However, if the LD which obtained the value to be compared was
KNOWN to be part of an ATOMIC sequence ending with CAS, one can
eliminate the ABA problem for all <reasonable> CAS sequences.
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               This can be implemented with LL/SC for sure.

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With the addition above.
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                                                            Scott
mentioned something about a bus lock after a certain amount of
failures... (side note) Weak CAS can fail even if the comparands are
identical to each other ala LL/SC. This reminds me of LL/SC. the ABA
problem can worked around and/or eliminated without using LL/SC. I
remember reading papers about LL/SC getting around ABA, but then read
about how they can have their own can of worms. Pessimistic vs
optimistic sync... Wait/ Lock / Obstruction free things... ;^)

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You are the expert on that here.
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Fwiw, getting rid of the StoreLoad membar in algorithms like SMR is
great. There is a way to do this in existing systems. So, no hardware
changes required, and makes the system run fast.

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I got rid of all MemBars and still have a fairly relaxed memory model.

 That is interesting to me! It's sort-of "out of the box" so to speak? How can a programmer take advantage of the relaxed aspect of your model?

 

Think of allowing a rouge thread to pound a CAS with random data wrt the
comparand, trying to get it to fail... Of course this can be modifying a
reservation granule wrt LL/SC side of things, right? Pessimistic (CAS)
vs Optimistic (LL/SC)?

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Or methodological (ESM).

 Still, how does live lock get eluded in your system? Think along the lines of a "rouge" thread causing havoc? Banging on cache lines ect... ;^o
 

Both are bad practice in making HW that can perform these things
efficiently. But notice that LL-SC does not have this problem.
Neither does ESM.
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According to my understanding, what matters is # of CPU cores with
coherent access to the same memory+IO.
For x86, 4 cores (CPUs) were relatively common since 1996. There
existed few odd 8-core systems too, still back in the last century.