Re: Is Intel exceptionally unsuccessful as an architecture designer?

On 9/23/2024 5:26 PM, MitchAlsup1 wrote:

On Mon, 23 Sep 2024 22:46:47 +0000, Chris M. Thomasson wrote:
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On 9/23/2024 3:32 PM, MitchAlsup1 wrote:

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I got rid of all MemBars and still have a fairly relaxed memory model.

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That is interesting to me! It's sort-of "out of the box" so to speak?
How can a programmer take advantage of the relaxed aspect of your model?
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Touch a DRAM location and one gets causal order.
Touch a MM I/O location and one gets sequential consistency
Touch a config space location and one gets strongly ordering
Touch ROM and one gets unordered access.
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You see, the memory <ordering> model is not tied to a CPU state, but
to what LD and ST instructions touch.

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What is the granularity of the "touch"? A L2 cache line?